Integrated circuits are often manufactured on a semiconductor substrate, such as a silicon wafer. The silicon wafer is typically a thin circular plate of silicon that is 150 or 200 or 300 millimeters in diameter and approximately 0.64 millimeters thick. Typically, a single wafer will have numerous devices which are integrated circuits formed on a lattice pattern. Each device consists of numerous layers of circuitry and a collection of external bonding pads. The bonding pads are small sites, typically 3 mils square, made usually with aluminum that eventually serve as the device's connections to the pin leads. The aluminum itself forms a thin non-conductive layer of aluminum oxide, which must be eliminated or broken through before good electrical contact can be made.
Since the packaging of a device is a costly procedure, it is desirable to test a device beforehand to avoid packaging faulty devices. The testing process involves establishing electrical contact between a device called a probe card and the wafer and then running a series of tests on the devices on the wafer's surface. The probe card has a collection of electrical contact pins that stand in for the normal pins and wire leads of a packaged device. The wafer is positioned relative to the probe card so that the contact pins on the probe card make contact with a wafer's bonding pads and a special tester runs a battery of electrical tests on the wafer's devices. A special machine, called a wafer prober, is used to position the wafer with respect to the probe card.
A wafer prober might be considered a three dimensional positioner. The primary purpose of wafer probing is to accurately position the wafer relative to the probe card in a manner that ensures that the wafer device's bonding pads make good electrical contact with a probe card's probe tips in order to properly test a device before dicing and packaging. High accuracy is required, because the devices' bonding pads on the wafer present a very small contact footprint and if a probe card pin were to make contact outside the bonding pad area, the result may be a break in the wafer's external surface layer, which generally results in a damaged device.
Of the three main processes required for good probing—wafer alignment, thickness profiling, and probe to pad alignment—only probe to pad alignment has not traditionally been automated. However, recent developments in semiconductor technology have driven a requirement for automation. In an effort to improve performance and to include more features on each device, sensitive components are being fabricated under the bond pads. Accurate positioning of the wafer substrate under the pins also enables shrinking of the pad size thereby allowing more room for the active circuitry. Accuracy and throughput issues have therefore led to the development of the automatic wafer prober.
There are several different considerations involved in wafer probing. Due to the thin layer of nonconductive oxide residue that forms over the bonding pad during normal atmospheric exposure, the probe tips must penetrate the residue and travel vertically beyond initial contact in order to make contact with the aluminum underneath. For instance, in the most common form of probe card technology, cantilever probes, a portion of this vertical over travel is transformed into motion along the plane of the wafer, or scrub, to further guarantee that the tip is in good contact with the underlying aluminum. In addition, the devices (with the exception of the bonding pads) are coated with an insulating layer of glass. If this glass layer is breached by the probe tips, the resultant cracks may damage an otherwise functional device. Therefore, a critical component of pad to probe alignment is the maintaining of an optimal relative (or contact) position between the probe card pins and the wafer pads. An optimal contact position is necessary to ensure that the exact required amount of contact pressure is exerted between the pins and a pad being tested. If too little pressure is exerted, insufficient contact is achieved and the prober cannot properly test because it may fail to break through the external oxide residue. If, on the other hand, too much pressure is exerted, damage to the pads may occur. Consequently, accurate positioning specifically along the contact load axes is a requirement for proper testing.
A further consideration for the maintenance of accurate contact positioning relates to the proper compensation of disturbances during operation. For instance, as the testing system runs the temperature of the system will be expected to change, and may do so at different levels for the different components making up the testing assembly. Temperature variations lead to relative expansion or contraction of the various components making up the system and in effect may change the previous relative (or contact) position between the pins and the pads. A disturbance in relative position can in turn lead to a change in the desired or commanded contact pressure between the pins and pad, which is of critical importance in maintaining proper performance.
However, prior art wafer prober systems do not provide thermal disturbance compensation. Current designs incorporate a drive and measurement mechanism situated at an appreciable distance from the wafer substrate locating surface. This method does not accurately and actively control the substrate surface during probing, especially at non-ambient temperatures.
In summary, recent advances in semiconductor technology have established a need for automatic probe to pad alignment during the testing process. In response, major vendors of wafer probers have offered some form of automatic probe to pad alignment. However, the existing forms of automatic alignment are often not sufficient to provide accurate alignment for modern integrated circuits that have very small and imperfectly shaped pads and probe tips and to ensure the maintenance of accurate relative positioning and contact in the presence of disturbances.